A Pipelined Multi-core MIPS Machine: Hardware Implementation by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul PDF

By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

ISBN-10: 3319139053

ISBN-13: 9783319139050

ISBN-10: 3319139061

ISBN-13: 9783319139067

This monograph relies at the 3rd author's lectures on desktop structure, given in the summertime semester 2013 at Saarland college, Germany. It includes a gate point building of a multi-core computer with pipelined MIPS processor cores and a sequentially constant shared memory.

The booklet comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and in addition of a cache dependent sequentially constant shared reminiscence. This opens tips to the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and therefore deterministic. by contrast the reference versions opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.

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Extra resources for A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof

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Thus, we have m(a) = 1 ↔ x = a . 6 (3) The term switching function comes from electrical engineering and stands for a Boolean function. 6 Boolean Algebra 27 We define the support S(f ) of f as the set of arguments a, where f takes the value f (a) = 1: S(f ) = {a | a ∈ Bn ∧ f (a)} . If the support is empty, then e = 0 computes f . Otherwise we set m(a) . 19) ↔ ∃a ∈ S(f ) : a = x (3) ↔ x ∈ S(f ) ↔ f (x) = 1 . Thus, equations e = 1 and f (x) = 1 have the same solutions. 16 we conclude e ≡ f (x) . 20 is called the complete disjunctive normal form of f .

For c ∈ N ∪ {−1} and t ∈ (e(c) + ρ, e(c + 1) + ρ], we define the register value x[i](t) and output at time t by a case split: • • Clocking the register at edges c ≥ 0. The clock enable signal is 1 at edge e(c) and the setup and hold times for the input and clock enable signals are met: x[i]ce(e(c)) ∧ stable(x[i]in, c) ∧ stable(x[i]ce, c) . Then the data input at edge e(c) becomes the new value of the register, and it becomes visible (at the latest) at time σ after clock edge e(c). Not clocking the register at edges c ≥ 0.

We denote this sequence of unknown binary values at startup by a[n − 1 : 0]: x−1 [n − 1 : 0] = a[n − 1 : 0] ∈ Bn . The current value of a circuit signal y in cycle t is defined according to the previously introduced circuit semantics: yt = in1(y)t in1(y)t ◦ in2(y)t y is an inverter y is a ◦-gate . Let x[n − 1 : 0]int and x[n − 1 : 0]cet be the register input and clock enable signals computed from the current configuration xt [n − 1 : 0] and the current value of the reset signal resett . , when the clock enable signal of register x[i] is active in cycle t, the register value of x[i] in cycle t + 1 is the value of the data input signal in cycle t; otherwise, the register value does not change.

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A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul


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