By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® describes the complicated ideas and methods used for ASIC chip synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the total ASIC layout movement technique distinct for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this booklet is on real-time program of Synopsys instruments used to strive against a number of difficulties visible at VDSM geometries. Readers may be uncovered to a good layout method for dealing with advanced, sub-micron ASIC designs. importance is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, and static timing research. At each one step, difficulties on the topic of every one section of the layout circulate are pointed out, with suggestions and work-arounds defined intimately. additionally, an important concerns with regards to format, along with clock tree synthesis and back-end integration (links to structure) also are mentioned at size. additionally, the ebook includes in-depth discussions at the fundamentals of Synopsys know-how libraries and HDL coding kinds, specific in the direction of optimum synthesis recommendations.
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® is meant for someone who's concerned with the ASIC layout technique, ranging from RTL synthesis to ultimate tape-out. objective audiences for this e-book are working towards ASIC layout engineers and graduate scholars project complicated classes in ASIC chip layout and DFT suggestions.
From the Foreword:
`This booklet, written via Himanshu Bhatnagar, offers a finished evaluate of the ASIC layout move special for VDSM applied sciences utilizing the Synopsis suite of instruments. It emphasizes the sensible concerns confronted via the semiconductor layout engineer by way of synthesis and the combination of front-end and back-end instruments. conventional layout methodologies are challenged and certain strategies are provided to aid outline the subsequent iteration of ASIC layout flows. the writer presents quite a few sensible examples derived from real-world occasions that may end up useful to working towards ASIC layout engineers in addition to to scholars of complicated VLSI classes in ASIC design'.
Dr Dwight W. Decker, Chairman and CEO, Conexant structures, Inc., (Formerly, Rockwell Semiconductor Systems), Newport seashore, CA, USA.
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Extra info for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®
A) b) c) d) e) Library Compiler Design Compiler and Design Analyzer PrimeTime Test Compiler Formality H.
An example design was used to guide the reader from start to finish. At each stage, brief explanation and relevant scripts were provided. The chapter started with basics of setting up the Synopsys environment and technical specification of the example design. Further sections were divided into pre-layout, floorplanning and routing, and finally the post-layout steps. The pre-layout steps included initial synthesis and scan insertion of the design, along with static timing analysis, and SDF generation for dynamic simulation.
However, the syntax and usage of the commands used by Formality will not be described. Formality may be used to verify RTL against RTL, RTL against synthesized gate-level netlist, or gate-level against gate-level netlist. At this point, Formality should be used to verify the RTL against synthesized netlist to check for the functional validity of the gate-level netlist. Compared to gatelevel simulation using the pre-layout SDF, Formality takes a fraction of time to completely verify the design. 4 Chapter 2 Floorplanning and Routing The floorplanning step involves physical placement of cells and clock tree synthesis.
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime® by Himanshu Bhatnagar