By Bart Vermeulen, Kees Goossens (auth.)
This publication describes an procedure and aiding infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), permitting its linked product to be brought into the industry extra fast. Readers research step by step the most important requisites for debugging a latest, silicon SOC implementation, 9 elements that complicate this debugging job, and a brand new debug strategy that addresses those requisites and complicating elements. The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug procedure is mentioned intimately, displaying the way it is helping to fulfill debug standards and handle the 9, formerly pointed out components that complicate debugging silicon implementations of SOCs. The authors additionally derive the debug infrastructure specifications to aid debugging of a silicon implementation of an SOC with their CSAR debug technique. This debug infrastructure includes a customary on-chip debug structure, a configurable automatic design-for-debug move for use throughout the layout of an SOC, and customizable off-chip debugger software program. insurance contains an review of the potency and effectiveness of the CSAR technique and its aiding infrastructure, utilizing six business SOCs and an illustrative, instance SOC version. The authors additionally quantify the rate and layout attempt to help their approach.
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Extra info for Debugging Systems-on-Chip: Communication-centric and Abstraction-based Techniques
3. 1 Behavior of a Single Building Block Formal Definitions Design teams commonly use an FSM description to specify the cycle-accurate behavior of an SOC building block [2, 3]. A block diagram of an FSM is shown in Fig. 1. The FSM in Fig. 1 has an input I , an internal state s, and an output O. The input I takes a value from the set I with a possible input symbols. The state takes its value from the set S with b possible states. The output O takes its value from the set O with c possible output symbols.
This so-called pipelining however adds a deterministic latency of a number of clock cycles to the communication of each data element. This reduces the performance and silicon area advantages of using a process technology with smaller geometries. Furthermore, guaranteeing that the constraint in Eq. 3 holds under all process variations and all operating conditions for all interacting flip-flop pairs becomes more difficult without increasing the clock period T . Increasing the clock period however again reduces the performance advantage of a process technology with smaller geometries.
The function u(t) is defined in Eq. 5 and shown graphically in Fig. 4. 2 Complicating Factors for Debugging Fig. 4 The time-quantization function u(t) 31 u(t) 2T + φ T+φ φ 0 0 φ T+φ 2T + φ 3T + φ t The dashed line in Fig. 4 shows the function v(t) = t. Note how the function u(t) stays below the function v(t) and yields the time of the closest preceding active edge for each time t. To calculate the next state value at each active edge, the current state of the FSM is combined with the momentary values on the input I of the FSM at the time of the last active edge, given by x(u(t)).
Debugging Systems-on-Chip: Communication-centric and Abstraction-based Techniques by Bart Vermeulen, Kees Goossens (auth.)